Switch Fabric on a Reconfigurable Chip using an Accelerated Packet Placement Architecture

Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirement dictated by output-queued switches while retaining their desirable performance characteristics. The high speed requirement from the memory management algorithm, which is responsible for placing arriving packets into non-conflicting memories, presents a fundamental challenge in implementing large PSM routers. In previous work, we have extended PSM results by introducing the concept of Fabric on a Chip (FoC). The latter advocates the consolidation of the core packet switching functions on a single chip. This paper further develops the underlying technology for high-capacity FoC designs by introducing a speedup factor coupled with a multiple packet placement process. This yields a substantial reduction in the overall memory requirements, paving the way for the implementation of large scale FoC-based platforms. We further provide detailed analysis for establishing an upper bound on the sufficient number of memories along with a description of an 80Gbps switch implementation on an Altera Stratix II FPGA. These results emphasize the scalability and performance attributes of the proposed architecture.